在AArch64状态下,哪种FPCR配置下的ARM FP指令符合IEEE 754-2008?

Under which FPCR configuration ARM FP instructions conform to IEEE 754-2008 in AArch64 state?

提问人:pmor 提问时间:6/5/2023 最后编辑:pmor 更新时间:6/6/2023 访问量:43

问:

一个简单的问题:在哪种 FPCR 配置 ARM FP 指令下符合 IEEE 754-2008?

我假设符合 IEEE 754-2008 的 FPCR 配置是:

- AHP (Alternative half-precision control bit): 0
- DN (Default NaN use for NaN propagation): 0
- FZ (Flushing denormalized numbers to zero control bit): 0
- RMode (Rounding Mode control field): 0 (Round to Nearest (RN) mode)
- Stride (This field has no function in AArch64 state): x (don't care)
- FZ16 (Flushing denormalized numbers to zero control bit on half-precision): 0
- Len (This field has no function in AArch64 state): x (don't care)
- IDE (Input Denormal floating-point exception trap enable): 0
- EBF (Controls the numeric behaviors of BFloat16 dot product calculations performed by the BFDOT, BFMMLA, BFMOPA, and BFMOPS instructions): x (don't care)
- IXE (Inexact floating-point exception trap enable): x (don't care)
- UFE (Underflow floating-point exception trap enable): x (don't care)
- OFE (Overflow floating-point exception trap enable): x (don't care)
- DZE (Divide by Zero floating-point exception trap enable): x (don't care)
- IOE (Invalid Operation floating-point exception trap enable): x (don't care)
- NEP (Controls how the output elements other than the lowest element of the vector are determined for Advanced SIMD scalar instructions): 0
- AH (Alternate Handling. Controls alternate handling of floating-point numbers): 0
- FIZ (Flush Inputs to Zero. Controls whether single-precision, double-precision and BFloat16 input operands that are denormalized numbers are flushed to zero): 0

这是对的吗?

IEEE-754 标准的 浮点 ARM FPU

评论

0赞 old_timer 6/5/2023
你问的时候,Arm说了什么?
0赞 pmor 6/6/2023
@old_timer 正如我所看到的,关于IEEE 754-2008的一致性,没有一个放之四海而皆准的声明。相反,有每个功能的语句。例如:“将非正规化刷新为零与 IEEE 754 标准不兼容,当需要 IEEE 754 兼容性时,不得使用”。因此,、 和 需要为 0。但是,并非所有 FP 功能都具有这些(或类似)语句。困惑(例如)。FZ16FZFIZ

答: 暂无答案