Verilog行为模型中的“->”是什么？

问：

我正在编写一个 i2c 主模块，并且我有 Microchip 提供的 Verilog AT24C02D模型，用于测试平台。我在代码中看到一些“->”;那是什么意思？

编号： https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/BoardDesignFiles/AT24C02D.v

//************************************************************************
//********************* S_START and S_STOP conditions ********************
//************************************************************************

// Start trigger allows latency between start condition and falling edge
// of SCL. If stop occurs in this interval the machine ignores the start
// condition and awaits a subsequent start condition.

  // START Condition Detection

  always @ (negedge SDA_in)
  if(SCL == 1) begin
    if (VERBOSE) $display("START condition detected", $time);
    S_STOP = 0;
    S_START = 1;
    -> START_condition;    // Start condition event

    if (VERBOSE) $display ("Got START condtion event");

    @(STOP_condition or negedge SCL)
    if (SCL == 0) begin
      if (VERBOSE) $display ("First negedge of SCL after START", $time);
      Valid_Address_flag = 0;
      if(VERBOSE) $display("START event triggered");
      -> START_trigger;    // Start trigger event
  @ (posedge SCL) S_START = 0;  // Waits until cycle ends
    end
    else begin    // STOP condition detected under same clock
      if (VERBOSE) $display ("STOP under same clock as START");
      S_START = 0;
      S_STOP = 1;
    end
  end

我成功地编译了文件。iverilog