我的代码上出现了以下错误，我不知道它们是什么意思，也不知道如何修复它们-解网

问：

所以我正在尝试在 EDA PLayground 上为 32 位 ALU 编写 VHDL，但我收到一些我不太明白的错误消息，我不知道如何修复它们，有人可以帮忙吗？我无法理解错误在哪里，也不知道在我的代码中要更改什么来修复它们。

以下是 VHDL 代码：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.ALL;

entity alu is
    port(
    A, B: in std_logic_vector(31 downto 0);
            opcode: in std_logic_vector(2 downto 0);
            Result: in std_logic_vector(31 downto 0) 
            );
end entity alu;

architecture dataoperations of alu is
begin 
    Result <= A + B when opcode="1010" 
    else    A - B when opcode="1000"
    else    abs(A) when opcode="1011"
    else    -A  when opcode="1101"
    else    abs(B) when opcode="0001"
    else    -B when opcode="1001"
    else    A or B when opcode="0110"
    else    not A when opcode="1111"
    else    not B when opcode="0101"
    else    A and B when opcode="1100"
    else    A xor B when opcode="0010";
end architecture dataoperations;

下面是测试台代码：

library IEEE;
use IEEE.std_logic_1164.all;

entity mytestbench is
end entity mytestbench;

architecture test of mytestbench is
    signal in1, in2, out1: std_logic_vector (31 downto 0);
    signal in3: std_logic_vector (2 downto 0);
begin
    g1: entity work.alu(dataoperations)
        port map (A <= in1, B <= in2; opcode <= in3, Result <= out1);
    in1 <= "0001", "0FAF" after 20 ns, "F000" after 40 ns;
    in2 <= "0100", "7FFF" after 10 ns, "FFFF" after 30 ns;
    in3 <= "00";
end architecture test;

以下是错误消息：

COMP96 File: design.vhd
COMP96 Compile Architecture "dataoperations" of Entity "alu"
COMP96 ERROR COMP96_0143: "Object "Result" cannot be written." "design.vhd" 15 2
COMP96 File: testbench.vhd
COMP96 ERROR COMP96_0724: "',' or ')' expected." "testbench.vhd" 12 28
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 12 31
COMP96 ERROR COMP96_0019: "Keyword 'when' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0016: "Design unit declaration expected." "testbench.vhd" 12 66
COMP96 ERROR COMP96_0019: "Keyword 'of' expected." "testbench.vhd" 16 22
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 16 22

VHDL 主动 HDL

-- in1 <= "0001", "0FAF" after 20 ns, "F000" after 40 ns;
    -- in2 <= "0100", "7FFF" after 10 ns, "FFFF" after 30 ns;
    -- in3 <= "00";
    in1 <= x"00000001", x"00000FAF" after 20 ns, x"0000F000" after 40 ns;
    in2 <= x"00000100", x"00007FFF" after 10 ns, x"0000FFFF" after 30 ns;
    in3 <= "000";

这并不是一个糟糕的第一次尝试。预计使用逗号的分号的错误量令人惊讶，这反映了 ALDEC 工具中的解析器架构。前瞻为 1 的解析器会（应该）更早退出。语法错误可能很难提供有用的错误消息，它们在进行任何语义分析之前就被检测到。您最后的办法可能是检查语法（在 LRM、IEEE 标准 1076 中描述）。

同一行上的第一个错误：

OMP96 ERROR COMP96_0724: "',' or ')' expected." "testbench.vhd" 12 28

其中最后两个数字是行号，字符位置是首先需要注意的。你几乎会认为在第一个错误后退出会更好，“教”你语言语法。

还有一个未公开的模拟错误，例如，字符串文字长度和操作码中的元素数不匹配（3、2 到 0）。相等运算符的计算结果将始终为 FALSE。要么修复字符串文字，要么在操作码中具有匹配数量的元素。when opcode="1010"

我的代码上出现了以下错误，我不知道它们是什么意思，也不知道如何修复它们

I have the following errors appearing on my code, I don't know what they mean neither know how to fix them

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